Algorithmic analog-to-digital converters (ADCs) often are used in low speed, high resolution applications in which power and silicon area are at a premium. In a typical implementation, a conventional algorithmic ADC uses the same conversion stage circuitry over a number of conversion cycles to produce a digital value representative of an input voltage. Conventional 1-bit algorithmic ADCs that generate one bit of the output digital value per conversion cycle are particularly susceptible to voltage offsets. To provide improved resilience to voltage offsets, circuit designers increasingly are implementing 1.5-bit algorithmic ADCs that generate the equivalent of approximately 1.5 bits of information for the output digital value per conversion cycle. These conventional 1.5-bit algorithmic ADCs define three voltage regions and each conversion cycle results in an output of a two-bit code that identifies the particular one of the three voltage regions in which the sampled voltage for the conversion cycle is found. The two-bit digital codes from the conversion cycles are combined to generate the output digital value.
Conventional 1.5-bit algorithmic ADC architectures employ two comparators to define the three voltage regions. Comparators require relatively large amounts of power and silicon area to implement. Moreover, the input signal being converted to a digital value often is a differential signal, thereby requiring the use of two differential difference comparators, which are complex to implement and often malfunction in the event that the common mode voltage of a reference voltage used to define the three voltage regions differs from the common mode voltage of the input signal. As such, conventional 1.5-bit algorithmic ADCs provide improved resilience to voltage offsets at the cost of increased complexity, power consumption, and silicon area.